The present invention relates generally to controlling power consumption in integrated circuit devices and, more particularly, to a three-terminal cascade switch for controlling static power consumption in integrated circuits.
Power consumption and heat generation in complementary metal oxide semiconductor (CMOS) integrated circuits is made up of a dynamic (or active) component and a static (or standby) component. Dynamic heat generation arises primarily from the charging and discharging of load capacitances during device switching, and is proportional to the system operating frequency. Presently, this component of power consumption is typically controlled by turning off the clock input signal to unused logic blocks.
On the other hand, static heat generation results from direct current (DC) flow through gates and other sources of current leakage, and is independent of operating frequency. In most digital logic circuits, dynamic power consumption is the dominant component while the chip is active. However, when the clock is stopped and a CMOS device enters a “sleep” mode to conserve power, static power consumption becomes the dominant component.
Because modern circuits are being designed with smaller and smaller gate thicknesses to improve performance, the resulting effect has been to boost the static power consumption component exponentially. FIG. 1 is a graph that illustrates the projected relative magnitudes of power consumption of the dynamic and static components as a function of decreasing feature size over time. As can be seen, the static heat component is increasing exponentially fast with respect to the dynamic source with decreasing feature size, and is expected to equal the dynamic heat production at a feature size of approximately 44 nanometers. Thus, unless a solution to the gate leakage problem is found, control of static heat sources in integrated circuits will become as essential as the control of dynamic power currently practiced.
Presently, static heat sources may be controlled by turning off the supply voltage to unused logic blocks (also referred to as “power gating”). Power gating is conventionally implemented by inserting a power level FET in the supply circuit of each isolatable logic block to enable control of its power supply. Unfortunately this approach occupies significant chip real estate due to the area of the power level FET, thereby incurring an area penalty for eliminating the static power dissipation.
Accordingly, it would therefore be desirable to be able to address the issue of stating power dissipation in a manner that overcomes the area penalty associated with conventional static power control means.